In contrast to traditional planar metal-oxide-semiconductor field-effect transistors (MOSFETs), which are fabricated using conventional lithographic fabrication methods, nonplanar field-effect transistors (FETs) incorporate various vertical transistor structures, and typically include two or more gate structures formed in parallel. One such semiconductor structure is the “FinFET,” which takes its name from the multiple thin “fins” that are used to form the respective gate channels, and which are typically on the order of tens of nanometers in width.
More particularly, referring to the exemplary prior art semiconductor structure shown in FIG. 1, a finFET 10 generally includes two or more parallel silicon fin structures (or simply “fins”) 12. The fins are typically formed on a semiconductor substrate 14 (FIG. 2) with the fin structures extending between a common drain electrode and a common source electrode (not shown). A conductive gate structure 16 “wraps around” three sides of fins 12, and is separated from the fins by a standard gate oxide layer 18. Fins 12 may be suitably doped to produce the desired FET polarity, as is known in the art, such that a gate channel is formed within the near surface of the fins adjacent to gate oxide 18.
FIG. 2 illustrates, in cross-section, a conventional semiconductor substrate 14 including a support substrate 20, a silicon oxide layer 22, and a silicon-comprising material layer 24 overlying the silicon oxide layer. The silicon-comprising material from which the fin structures are formed and the silicon oxide layer form a silicon on insulator (SOI) structure 26 that, in turn, is supported by the support substrate 20. Fins may be formed using any conventional process, including but not limited to, conventional photolithographic and anisotropic etching processes (e.g. reactive ion etching (RIE) or the like). After formation and cleaning of the fins, FinFET processing steps may include forming the gate structure(s) 16, ion implantation, and source/drain (S/D) epitaxy modules.
Unfortunately, semiconductor structure processing steps performed subsequent to fin formation can create defects in the fins, and/or can cause portions of the fins to become eroded. These defects and eroded fins can compromise the performance of semiconductor devices in which they are ultimately used.
Thus, a need exists for improved semiconductor structures and methods of making the same, which allow for the integrity of the fin structures to be better preserved during semiconductor fabrication. Other desirable features and characteristics of the present invention will become apparent from the following detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.
While certain aspects of conventional technologies have been discussed to facilitate disclosure of the invention, Applicant in no way disclaims these technical aspects, and it is contemplated that the claimed invention may encompass one or more of the conventional technical aspects discussed herein.
In this specification, where an act or item of knowledge is referred to or discussed, this reference or discussion is not an admission that the act or item of knowledge or any combination thereof was, at the priority date, publicly available, known to the public, part of common general knowledge, or otherwise constitutes prior art under the applicable statutory provisions; or is known to be relevant to an attempt to solve any problem with which this specification is concerned.